As integrated circuits (ICs) have continued to become faster, smaller, and more complex, the ability to test them has become more difficult but, at the same time, such testing has become more critical. Integrated circuit designers and manufacturers have come to realize that in order to assure the integrity of their products, high-quality, and cost effective testing must be implemented.
In the past, “bed-of-nails” testers were appropriate where the board-under-test was available to be lowered onto a set of test points (nails) that probe points of interest on the board. These could be sensed (observed) and driven (controlled) to test the complete board. The increasing complexity of boards and the movement to technologies such as nanometer designs, multi-chip modules (MCMs), and surface mount technologies (SMTs) made the bed-of-nails approach ineffective as fewer and fewer nodes on a chip could be externally accessed.
Nevertheless, the concepts of observability and controllability continue to be fundamental in being able to properly test a circuit. In an optimum situation, a circuit can be fully observed and fully controlled. In actual application, both observability and controllability are often limited, sometimes severely, especially in highly integrated circuits.
Scan techniques offer the ability to better observe and control these more complex chips. For example, boundary scan techniques offer the ability to test boundary circuitry of an IC, e.g., circuitry within the IC that directly interfaces with a printed circuit board. Also, internal scan techniques are used to test the circuitry that can be deep within the IC. Each of these techniques will be briefly described to provide context to the present invention.
As is the case in many situations, the adoption of a standard facilitated an industry implementation. In the case of boundary scan, system designers agreed on a unified scan-based methodology that are set forth in IEEE STD 1149.1, 0.4, and 0.6, which are incorporated herein for all purposes. Boundary scan was originally developed by the Joint Test Access Group and is often called JTAG.
The basic architecture of IEEE STD 1149.1 boundary scan is incorporated at the integrated circuit level as shown in FIG. 1. The I/O pins 102 of each IC on the board are connected serially in a standardized scan chain 104 accessed through the Test Access Port (TAP) 106 so that every pin 102 can be observed and controlled remotely through scan chain 104. At the board level, IC 108 can be connected in series with other ICs to form a scan chain 104 spanning the entire board containing multiple ICs. Connections to IC 108 are tested by scanning values into the outputs of each IC 108 and checking that those values are received at the inputs of the IC 108. IC 108 with internal scan chain 104 and BISTs can access those features through the boundary scan technique to provide a unified testing framework.
A key feature of the IEEE STD 1149 boundary scan technique is the implementation of a Test Access Port (TAP) 106. TAP 106 includes four, or optionally five or more, single bit connections. These connections interface with certain on-chip boundary scan logic to implement a communication protocol. The communication protocol used for boundary scan is driven by TCK 120 and TMS 122 and, optionally, TRST 130. TCK 120 is a Test Clock input that is used to, among other things, shift data into and out of ICs 108. TMS 122 is a Test Mode Select input that controls the types of test operations to be conducted. TDI 124 is a Test Data In that inputs the test data and instructions to be used by the IC 108 during testing. TDO 126 is a Test Data Out output that includes the results of the testing. This output is driven only when TAP controller 128 is in the shift TAP controller state, Shift-DR or Shift-IR. Optional TRST 130 is a Test Reset Signal input that is an active low signal that asynchronously resets the TAP controller 108 if no power-up reset signal is automatically generated by IC 108.
When the IC 108 is in a normal mode, TRST 130 and TCK 120 are held low and TMS 122 is held high in order to disable boundary scan. To prevent race conditions, inputs are sampled on the rising edge of TCK 120 and outputs toggle on the falling edge.
TAP controller 128 is typically a 16-state FSM that proceeds from state to state based on TCK 120 and TMS 122 signals. It provides signals that control a test data register and an instruction register. These include serial shift clocks and update clocks.
A state transition diagram 200 for the TAP controller 129 is shown in FIG. 2. The TAP controller 128 is initialized to Test-Logic-Reset 202 on power-up by TRST or by an internal power-up detection circuit. TAP controller 128 moves from one state to the next on the rising edge of TCK 120 based on the value of TMS 122. A typical test sequence will involve clocking TCK 120 and setting TRST 130 to 0 for a few cycles and then returning this signal to 1 to reset the TAP controller 108. TMS 130 is then toggled to traverse the state machine for whatever operation is required.
The transition diagram 200, as shown in FIG. 2, provides the roadmap for IEEE STD 1149.1 applications. Each state contains a label with a designated path that depends on the state of TMS 130 at the rising edge of TCK 120. The two vertical columns 204 and 206 each containing seven states that are substantially similar. Column 204 is the data column that makes use of a data register and column 206 is the instruction column that makes use of an instruction register. By traversing the states of column 204, data can be manipulated in IEEE STD 1149.1 testing, and by traversing the states of column 206, instructions can be called out for execution. Operations can include, for example, serially loading an instruction register or serially loading or reading data registers that are used to test interconnections between chips on a board.
More generally, scan techniques can be implemented to test almost any internal circuitry within an IC. To do this, storage elements within an IC are replaced with scan cells. For example, as shown in FIG. 3, where an IC may have multiple storage elements such as D flip-flop storage element 302, such storage elements can be replaced with scan cells 350.
Storage element 302 is shown with inputs D 304, Q 306, and CK 308. In a typical application, the signal at D 304 is output to Q 306 upon the rising edge of clock signal CK 308. Storage elements 302-1, 302-2, and 302-3 can be found throughout an integrated circuit as shown in FIG. 3 to facilitate the operation of combinational logic 310.
Scan cell 350 is more complex than storage element 302 with the addition of multiplexer 352 but operates similarly to storage element 302 during normal operation. In normal operation of scan cell 350 when scan enable SE 354 is set low, the signal at DI 356 is directed to input D 358 and output to Q/SO 360 upon the rising edge of clock signal CK 362. In this way, the implementation of scan cells 350-1, 350-2, and 350-3 with scan enable SE 372 set low allows for the operation of combinational logic 366 to be substantially similar to the operation of combinational logic 310.
Scan cell 350, however, allows for the scanning in and scanning out of data. For example, during a scan-in operation when scan enable SE 354 is set high, scan-in data SI 364 is directed to input D 358 and output to Q/SO 360 upon the rising edge of clock signal CK 362. In this way, test data can be scanned into the internal circuitry of an IC.
The combinational logic 366 of the IC can then operate using such test data and the result can be stored in the same scan cells 350. For example, scan cells 350-1, 350-2, and 350-3 can be configured as a scan chain 368 where data is scanned in through SI 370 by shifting data from scan cell 350-1 to scan cell 350-2 and then to scan cell 350-3 using clock signal 374 when scan enable SE 372 is set high, which is known as Scan Shift Cycle. When all the test data is scanned in, scan enable SE 372 is set low and a test operation can be launched to operate combinational logic 366 under the desired test input. Upon completion of the test, results are stored in scan cells 350-1, 350-2, and 350-3 by applying a clock signal 374 when scan enable SE 372 is set low, which is known as Scan Capture Cycle. The test data can then be scanned out to scan out SO 376 through the use of clock CK 374 when scan enable SE 372 is set high.
With this fundamental understanding of scan testing, the problems associated with such testing can be better understood. As described above, one clock signal is used to drive the test circuitry. The frequency of this capture clock signal is fixed such that for any given test set for the given IC, only one set of test clock frequencies can be used.
With this limitation, a designer that is required to test a complex integrated circuit with many features is limited to one clock frequency for testing the entire circuit. In general, shift operations are performed at a slow speed in order to reduce excessive simultaneous switching noise that can cause shift operations to fail. More precisely, during the Capture Cycle, depending on the delays in the combinational logic 366, different clock frequencies can be used to capture signals at the functional speed. Test and scan pattern generation tools known as ATPG (Automation Test Pattern Generation) have a limitation to use more than one clock frequency for the given test set for the circuit under test (CUT). If a different clock speed is required, another test set for the CUT has to be created such that each clock speed requires its own test set for the CUT. These discrepancies limit the quality of test; add cost and complexity to the test, and provide non-ideal conditions for modern devices.
Where a clock frequency is low, certain circuitry within the IC may not be appropriately exercised. But in using a higher clock frequency, certain circuitry may be appropriately tested but certain other circuitry may be unnecessarily over tested. It may be the case that for this certain other circuitry, real-world applications would never similarly exercise the circuits in terms of speed. The result may, therefore, be that a designer is forced to use a clock frequency that assures proper operation of the whole circuit but that may unnecessarily overstress certain parts of the integrated circuit. When implemented at this clock frequency, some or many good ICs may be discarded. Conversely, some or many ICs may incorrectly pass.
Especially with the increasing complexity of modern chips with their increased functionality and higher operating speed, the use of one clock frequency for the testing of the entire IC may not be appropriate. Essentially, one test clock frequency may not be appropriate for all the cells in an IC. It is therefore desirable to have a scan application where the clock frequency may be adapted for testing of specific cells in an IC. For example, a highly complex cell that includes highly integrated digital signal processor circuitry may require a high test clock frequency to assure proper operation. But a less complex standard logic cell may not need to be stressed at high clock rates because it will never experience such stresses. In providing a test apparatus with a variable test clock frequency, an entire integrated circuit design process can be improved while assuring the at-speed functionality of the integrated circuits.
As test vector size increases, there are more demands to reduce test time while simultaneously maintaining the same or better test coverage. Because the scan test vector creates circuit disturbances during scan shift operation and test launch cycle, optimally, a slow speed shift operation is used during scan shift cycles. These disturbances are due to simultaneous switching activities cause by the shifting operation of scan data through the scan chain. During the at-speed scan test capture where time between the launch and the capture time is critical to detect at-speed delay defects, similar disturbances are also present. But for the test launch cycle to perform the at-speed test, reducing the test speed is necessary to avoid the simultaneous switching noises that would defeat the purpose of testing the device at-speed. The effects of the disturbances are often noted to the signal as a slow to propagate condition due to delays in switching circuitry from di/dt related ground noise and changes in slew rate from IR drop. These phenomenon starts to cause over test conditions during at-speed test using the scan vectors. Study of this issue shows that for the same signal path there are different signal propagation speeds due to the different simultaneous switching noises. A solution to this over test condition is to reduce a correct amount of delay caused by the disturbances from the at-speed launch.